1. Field of the Invention
The invention relates in general to a non-volatile memory and an operating method thereof, and more particularly to a non-volatile memory having an improved erased phenomenon, and an operating method thereof.
2. Description of the Related Art
The current electronic device usually has a non-volatile memory for storing a lot of data. In order to process and store the information, the non-volatile memory must have the function of programming or erasing array cells in a flash memory.
FIG. 1 (Prior Art) is a schematic illustration showing a conventional non-volatile memory 10. Referring to FIG. 1, the non-volatile memory 10 includes a memory cell array 110, dummy cell arrays 122, word lines 160 and bit lines 150. The dummy cell arrays 122 are disposed on two sides of the memory cell array 110, and the memory cell array 110 and the dummy cell arrays 122 are respectively composed of memory cells 1122 and dummy cells 1222. The memory cells 1122 and the dummy cells 1222 are respectively coupled to the bit lines 150, and are respectively controlled by the word lines 160.
Each of the memory cell 1122 and the dummy cell 1222 may be a transistor having an oxide-nitride-oxide (ONO) structure. Thus, data can be stored in the ONO structure of the transistor in the form of charges. The method of programming the transistor may be implemented by injecting channel hot electrons (CHEs) into the ONO structure. The erasing operation may be implemented by way of hot hole injection (HHI), which is generated by the band-to-band tunneling, into the ONO structure. When the data stored in the ONO structure is ready to be read, the current flowing through the drain and the source of the transistor is sensed by sense amplifier. The charges may be stored in the ONO structure on two connection edges of the channel layer of the transistor, so the transistor may store two bits of data.
However, the dummy cell 1222 adjacent to the memory cell 1122 is in the erased state for a long time, so the over erase phenomenon tends to occur. When the over erase phenomenon occurs, a bit line to bit line current leakage lleak flows through the dummy cell 1222 adjacent to the memory cell 1122 and thus influences the read result in reading period of the non-volatile memory.
FIG. 2 (Prior Art) is a schematic illustration showing a program method of the conventional non-volatile memory. Referring to FIG. 1, the program method of the conventional non-volatile memory includes the following steps. First, as shown in step 510, the main array program sequence start to be operated. Wherein, the main array is such as the memory cell array 110. Next, as shown in step 520, the main array is programmed. Then, as shown in step 530, main array passes program verification. Next, as shown in step 540, the main array program sequence is ended. Then, as shown in step 550, the boundary bit program sequence start to be operated. Next, as shown in step 560, the threshold voltage Vth of the boundary bit is programmed to a very high voltage level by a strong program bias voltage without verifying. Wherein, the boundary bit is such as one end of the dummy cell 1222 adjacent to the memory cell 1122. Then, as shown in step 570, the boundary bit program sequence is ended.